1. Field of the Invention
The present invention relates to an active load circuit for use in a differential amplifier and the like, and more particularly to an active load circuit for use in a differential amplifier of the input stage of an operational amplifier.
2. Description of the Related Art
As a measure for reducing the current consumption in the circuitry of operational amplifier while widening the output amplitude thereof into the range of power supply voltage (VDD) to assure the capability of output current, an operational amplifier has been proposed which uses MOS transistors for both source and sink of the output stage. This type of operational amplifier attempts to eliminate the limitation of output amplitude in case that the output transistors are made of bipolar type transistor, require not large bias current, which might be needed when the source or sink of the output stage is made of constant current circuit or bipolar transistors, in order to achieve compatibility in the capability of output current and in the lower consumption current.
FIG. 1 shows an operational amplifier 100 in accordance with the Prior Art. This circuit is an example constituted of MOS transistors. For the differential current flowing through active load transistors Tr101 and Tr103 in the input differential amplifier stage, a current mirror circuit passes the positive input of differential current from the transistor Tr101 to a transistor Tr105, and then from a transistor Tr106 to a transistor Tr108 and another transistor Tr112. The current mirror also passes the negative input of differential current from the transistor Tr103 to a transistor Tr111. Then, the voltage developed from the difference in current between the transistor Tr112 and the transistor Tr111 may be applied to the gate of an output sink transistor Tr114 as well as to the gate of a transistor Tr110 in an output idling current setting circuit, which circuit is formed of transistors Tr107, Tr108, Tr109 and Tr110. In the output idling current setting circuit, transistors Tr107 and Tr109, and transistors Tr108 and Tr110 are of the same types, which may act as a kind of differential circuit. Due to the feedback operation in the system including the operational amplifier 100, in the constant condition, gate voltages of transistors Tr110 and Tr108 may be controlled to be at the same potential and so may drain voltages of the transistors Tr110 and Tr108. The drain of the transistor Tr108, hence the drain of the transistor Tr107 and the drain of the transistor Tr109 may be at the same potential, which potential may be applied to the gate of an output source transistor Tr113.
The gate-source voltage of the output source transistor Tr113 and the transistor Tr109 may become equivalent, so that the current in correspondence with the ratio of gate size of the output source transistor Tr113 to the transistor Tr109 may be drawn as the output stage bias current for compensating for the cross-over distortion in the output stage. The current level of the transistor Tr109 in the output idling current setting circuit may be set by the current ratio of the transistor Tr108 and the transistor Tr110 with respect to the transistor Tr106. By setting this current level to an appropriate value, the bias current flowing through the output stage is suppressed so as to achieve a lower consumption current rate.
However, in the structure of the Prior Art operational amplifier 100, a number of current mirror circuits may be required, because the source/sink transistors tr113 and tr114 in the output stage formed by MOS transistors are biased, by using a current mirror circuit for switching the differential current flowing through the active load transistors Tr101 and Tr103 in the input differential amplifier stage. More specifically, a current mirror circuit such as the transistor Tr101 and the transistor Tr105 for the differential input current in the positive input, the transistor Tr103 and the transistor Tr111 for the differential input current in the negative input, and the transistor Tr106 and the transistor Tr112 for setting bias for the transistor Tr114 for output sink transistor and the like may be required. In such circuits differential pair Tr102 and Tr104 and the active load pair Tr101 and Tr103 in the input differential amplifier stage, as well as the identity of paired transistors may define the accuracy of the operational amplifier 100, therefore the difference in the characteristics between these transistors may cause the dispersion of offset in the operational amplifier 100 to be aggravated. In other words, the dispersion factor may be composed of five sets of circuits in total, including three sets of current mirror circuits plus two sets in the input differential amplifier stage, resulting in a problem that the offset dispersion may be enlarged in the architecture of the operational amplifier 100.
The construction of multi-stage cascading by the current mirror circuits may require a long time for input/output response, resulting in that another problem that the circuitry may not accelerate the response.
The present invention has been made in view of the above circumstances and to overcome the above problems and has an object to provide an active load circuit, which is suitable for achieving an operational amplifier circuit, which may cope with both output current capability and lower consumption current, with less offset, and may be capable of operating at higher speed in case of transient response.
In order to achieve the foregoing object, the active load circuit in accordance with one aspect of the present invention comprises two current mirror circuits including a first current mirror circuit and a second current mirror circuit, both reference potential connection terminals of the current input transistor in one current mirror circuit and of the current output transistor in another current mirror circuit are paired to route to one end of a first impedance circuit and a second impedance circuit, respectively, then the other end of the first and second impedance circuits are connected to the reference potential.
In the active load circuit as have been described above, when outputting differential output current from the first and second output terminals of the first and second current output transistors in the first and second current mirror circuits in response to the differential input current received at the first and second input terminals of the current input transistors in the first and second current mirror circuits, the differential input current will flow through the first and second impedance circuits, and then the difference in voltage drop in correspondence with the differential component in the differential input current will appear in the first and second impedance circuits, which voltage drop will be applied to the reference voltage connection terminal of the output transistor in the other current mirror circuit.
Only when the differential input current has differential component, the voltage drop in the impedance circuit connected to the circuit having the larger differential component will become larger than the voltage drop in the other impedance circuit, and as the terminal voltage at the reference potential connection terminal of the other output current transistor connected to this impedance circuit will be applied with lower voltage than the terminal voltage of the reference potential connection terminal of the output current transistor of the one impedance circuit, the active load circuit will increase the current driving performance of the output current transistor while decreasing the current driving performance of the output current transistor in the other circuit. Therefore a differential output current amplified to a current rate more than the rate defined by the mirroring ratio in the current mirror circuit may be obtained in correspondence with the magnitude of the differential component in the differential input current. By using this active load circuit as the active load circuit of an operational amplifier circuit, the differential output current may be amplified only when the operational amplifier becomes transient status and consequently the differential input current has the differential component, allowing a high-speed performance of the transient response.
In case in which there is dispersion in the characteristics among the elements of the active load circuit, a certain offset may appear in the differential input current because the differential output current are to be balanced. However, by adding the impedance circuit, the amplifying effect of the differential output current works depending on the differential component in the differential input current. Since differential output current may be far from balancing at the balance point the same to the case without impedance circuit whereby the offset of the differential input current can be narrow, the active load circuit in accordance with the present invention used in the operational amplifier may minimize the dispersion of offset.
In order to achieve the object as have been described above, the operational amplifier in accordance with another aspect of the present invention comprises an active load circuit in the input differential stage including two current mirror circuits made of a first current mirror circuit and a second current mirror circuit, both reference potential connection terminals of the current input transistor in one current mirror circuit and of the current output transistor in another current mirror circuit are paired to route to one end of a first impedance circuit and a second impedance circuit, respectively, then the other end of the first and second impedance circuits are connected to the reference potential.
In the operational amplifier as have been described above, when outputting differential output current from the first and second output terminals of the first and second current output transistors in the first and second current mirror circuits in response to the differential input current received at the first and second input terminals of the current input transistors in the first and second current mirror circuits, the differential input current will flow through the first and second impedance circuits, and then the difference in voltage drop in correspondence with the differential component in the differential input current will appear in the first and second impedance circuits, which voltage drop will be applied to the reference voltage connection terminal of the output transistor in the other current mirror circuit, therefore served as the active load circuit in the input differential stage.
In an operational amplifier having the active load circuit, only when the differential input current has differential component, the voltage drop in the impedance circuit connected to the circuit having the larger differential component will become larger than the voltage drop in the other impedance circuit, and as the terminal voltage at the reference potential connection terminal of the other output current transistor connected to this impedance circuit will be applied with lower voltage than the terminal voltage of the reference potential connection terminal of the output current transistor of the one impedance circuit, the active load circuit will increase the current driving performance of the output current transistor while decreasing the current driving performance of the output current transistor in the other circuit. Therefore a differential output current amplified to a current rate more than the rate defined by the mirroring ratio in the current mirror circuit may be obtained in correspondence with the magnitude of the differential component in the differential input current. Therefore when the operational amplifier is in the transient state, the bias current for the next stage and following may be amplified, allowing a high-speed performance of the transient response.
In addition, the amplification effect of the differential output current in response to the differential component in the differential input current may remedy dispersion in the characteristics among the elements of the active load circuit.
The above and further objects and novel features of the present invention will more fully appear from following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and not intended as a definition of the limits of the present invention.